create_clock -period 20 CLOCK_50
derive_clocks -period 20
derive_clock_uncertainty

set_input_delay -clock CLOCK_50 -max 0 [get_ports {SW[*]}]
set_input_delay -clock CLOCK_50 -min 0 [get_ports {SW[*]}]
set_input_delay -clock CLOCK_50 -max 0 [get_ports {KEY[*]}]
set_input_delay -clock CLOCK_50 -min 0 [get_ports {KEY[*]}]

set_output_delay -clock CLOCK_50 -max 0 [get_ports {LEDR[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {LEDR[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {LEDG[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {LEDG[*]}]

set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX0[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX0[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX1[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX1[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX2[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX2[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX3[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX3[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX4[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX4[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX5[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX5[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX6[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX6[*]}]
set_output_delay -clock CLOCK_50 -max 0 [get_ports {HEX7[*]}]
set_output_delay -clock CLOCK_50 -min 0 [get_ports {HEX7[*]}]

set_false_path -from [get_ports {SW[*]}]
set_false_path -from [get_ports {KEY[*]}]

set_false_path -from * -to [get_ports {LEDR[*]}]
set_false_path -from * -to [get_ports {LEDG[*]}]
set_false_path -from * -to [get_ports {HEX0[*]}]
set_false_path -from * -to [get_ports {HEX1[*]}]
set_false_path -from * -to [get_ports {HEX2[*]}]
set_false_path -from * -to [get_ports {HEX3[*]}]
set_false_path -from * -to [get_ports {HEX4[*]}]
set_false_path -from * -to [get_ports {HEX5[*]}]
set_false_path -from * -to [get_ports {HEX6[*]}]
set_false_path -from * -to [get_ports {HEX7[*]}]

set_input_delay  -clock CLOCK_50 -max 0.5 [get_ports {SRAM_DQ[*]}]
set_input_delay  -clock CLOCK_50 -min 0.5 [get_ports {SRAM_DQ[*]}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_DQ[*]}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_DQ[*]}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_ADDR[*]}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_ADDR[*]}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_CE_N}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_CE_N}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_WE_N}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_WE_N}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_OE_N}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_OE_N}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_LB_N}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_LB_N}]
set_output_delay -clock CLOCK_50 -max 0.5 [get_ports {SRAM_UB_N}]
set_output_delay -clock CLOCK_50 -min 0.5 [get_ports {SRAM_UB_N}]
